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13.4.2 DMAC bus cycle state transition
Except for the block transfer mode, each time the processing for a DMA transfer is completed, the bus mastership
is released.
Figure 13-1. DMAC Bus Cycle (Two-Cycle Transfer) State Transition
CHAPTER 13 DMA FUNCTIONS (DMA CONTROLLER)
TI
T0
T1R
T2R
T1W
T2W
TE
TI
Preliminary User's Manual U15905EJ1V0UD
T1RI
T2RI
T1WI
413
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