NEC V850ES/SA2 UPD703201 Manual page 224

ALVn
0
1
The initial value of the ALVn bit is 1.
ETIn
0
1
• When ETIn = 0, the count clock can be selected according to the CSn2 to CSn0
bits of TMCn0.
• When ETIn = 1, the valid edge can be selected according to the TESn1 and
TESn0 bit specifications of SESn.
CCLRn
0
1
ECLRn
0
1
CMSn1
0
1
CMSn0
0
1
Remark A reset takes precedence for the flip-flop of the TOn output (n = 0, 1).
224
CHAPTER 7 TIMER/COUNTER FUNCTION
External pulse output (TOn) active level specification
Low level
High level
Count clock external/internal switch specification
Specifies the input clock (internal).
Specifies the external clock (TIn0).
TMn register clear enable/disable specification during compare operation
Clearing is disabled
Clearing is enabled (if CCn0 and TMn match during a compare operation,
TMn is cleared)
TMn register clear enable/disable specification by external clear input (TCLRn)
Clearing is disabled
Clearing is enabled (after clearing, counting is restarted)
Capture/compare register (CCn1) operation mode selection
The register operates as a capture register.
The register operates as a compare register.
Capture/compare register (CCn0) operation mode selection
The register operates as a capture register.
The register operates as a compare register.
Preliminary User's Manual U15905EJ1V0UD
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