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(3) Asynchronous serial interface transmission status register n (ASIFn)
The ASIFn register, which consists of 2 status flag bits, indicates the status during transmission.
By writing the next data to the TXBn register after data is transferred from the TXBn register to the transmit
shift register, transmit operations can be performed continuously without suspension even during an interrupt
interval. When transmission is performed continuously, data should be written after referencing the TXBFn bit
of the ASIFn register to prevent writing to the TXBn register by mistake.
This register is read-only, in 8-bit or 1-bit units.
After reset:
ASIFn
TXBFn
• When transmission is performed continuously, data should be written to the
TXSFn
• When the transmission unit is initialized, initialization should be executed after
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CHAPTER 12 SERIAL INTERFACE FUNCTION
00H
R
Address:
FFFFFA05H, FFFFFA15H
7
6
5
0
0
0
0
Data to be transferred next to the TXBn register does not exist (when
the ASIMn register's POWERn or TXEn bit is 0, or when data has been
transferred to the transmit shift register)
1
Data to be transferred next exists in the TXBn register (data exists in
the TXBn register when the TXBn register has been written to)
TXBn register after confirming that this flag is 0. If writing to the TXBn register is
performed when this flag is 1, transmit data cannot be guaranteed.
Transmit shift register data flag
(indicating the transmission status of UARTn)
0
Initial status or a waiting transmission (when the ASIMn register's
UARTCAEn or TXEn bit is set to 0, or following transfer completion, the
next data transfer from the TXBn register is not performed)
1
Transmission in progress (when data has been transferred from the
TXBn register)
confirming that this flag is 0 following the occurrence of a transmission
completion interrupt. If initialization is performed when this flag is 1, transmit
data cannot be guaranteed.
Preliminary User's Manual U15905EJ1V0UD
4
3
2
0
0
0
TXBFn
Transmit buffer data flag
<1>
<0>
TXSFn
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