Subclock Operation Mode; Setting And Operation Status; Releasing Subclock Operation Mode - NEC V850ES/SA2 UPD703201 Manual

32-bit single-chip microcontrollers
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15.6 Subclock Operation Mode

15.6.1 Setting and operation status

The subclock operation mode is set when the CK3 bit of the processor clock control register (PCC) is set to 1 in the
normal operation mode.
When the subclock operation mode is set, the internal system clock is changed from the main clock to the
subclock.
When the MCK bit of the PCC register is set to 1, the operation of the main clock oscillator is stopped. As a result,
the system operates only with the subclock. However, watchdog timer stops counting when subclock operation is
started (CLS bit of PCC register = 1). (Watchdog timer retains the value before the subclock operation mode was
set.)
In the subclock operation mode, the current consumption can be reduced to a level lower than in the normal
operation mode because the subclock is used as the internal system clock. In addition, the current consumption can
be further reduced to the level of the software STOP mode by stopping the operation of the main system clock
oscillator.
Table 15-8 shows the operation status in subclock operation mode.
Caution When manipulating the CK3 bit, do not change the set values of the CK2 to CK0 bits of the PCC
register (using a bit manipulation instruction to manipulate the bit is recommended). For details
of the PCC register, refer to 6.3 (1) Processor clock control register (PCC).

15.6.2 Releasing subclock operation mode

The subclock operation mode is released by RESET pin input when the CK3 bit is cleared to 0. If the main clock is
stopped (MCK bit = 1), set the MCK bit to 1, secure the oscillation stabilization time of the main clock by software, and
clear the CK3 bit to 0.
The normal operation mode is restored when the subclock operation mode is released.
Caution When manipulating the CK3 bit, do not change the set values of the CK2 to CK0 bits (using a bit
manipulation instruction to manipulate the bit is recommended).
For details of the PCC register, refer to 6.3 (1) Processor clock control register (PCC).
458
CHAPTER 15 STANDBY FUNCTION
Preliminary User's Manual U15905EJ1V0UD

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