Watchdog Timer - Atmel ATtiny25 Manual

8.9

Watchdog Timer

7598H–AVR–07/09
ADC is used. To reduce power consumption in Power-down mode, the user can avoid the three
conditions above to ensure that the reference is turned off before entering Power-down mode.
Table 8-4. Internal Voltage Reference Characteristics
Symbol Parameter
V Bandgap reference voltage
BG
t Bandgap reference start-up time
BG
Bandgap reference current
I
BG
consumption
The Watchdog Timer is clocked from an On-chip Oscillator which runs at 128 kHz. By controlling
the Watchdog Timer prescaler, the Watchdog Reset interval can be adjusted as shown in
8-7 on page 43. The WDR – Watchdog Reset – instruction resets the Watchdog Timer. The
Watchdog Timer is also reset when it is disabled and when a Chip Reset occurs. Ten different
clock cycle periods can be selected to determine the reset period. If the reset period expires
without another Watchdog Reset, the ATtiny25/45/85 resets and executes from the Reset Vec-
tor. For timing details on the Watchdog Reset, refer to
The Wathdog Timer can also be configured to generate an interrupt instead of a reset. This can
be very helpful when using the Watchdog to wake-up from Power-down.
To prevent unintentional disabling of the Watchdog or unintentional change of time-out period,
two different safety levels are selected by the fuse WDTON as shown in Table 8-5. Refer to
"Timed Sequences for Changing the Configuration of the Watchdog Timer" on page 44
details.
Table 8-5. WDT Configuration as a Function of the Fuse Settings of WDTON
Safety
WDTON Level
Unprogrammed
Programmed
Figure 8-7. Watchdog Timer
V
WDT Initial
State
1 Disabled
2 Enabled
128 kHz
OSCILLATOR
WATCHDOG
RESET
WDP0
WDP1
WDP2
WDP3
WDE
ATtiny25/45/85
Condition Min
= 1.1V / 2.7V,
CC
1.0
T = 25°C
A
V = 2.7V,
CC
T = 25°C
A
V = 2.7V,
CC
T = 25°C
A
Table 8-7 on page
How to Disable the
WDT
Timed sequence
Always enabled
WATCHDOG
PRESCALER
MCU RESET
Typ Max Units
1.1 1.2 V
40 70 µs
15 µA
Table
43.
for
How to Change
Time-out
No limitations
Timed sequence
41