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3.
AVR CPU
3.1
Features
3.2
Overview
3.3
Architectural Overview
8210C–AVR–09/11
•
8/16-bit, high-performance Atmel AVR RISC CPU
– 142 instructions
– Hardware multiplier
•
32x8-bit registers directly connected to the ALU
•
Stack in RAM
•
Stack pointer accessible in I/O memory space
•
Direct addressing of up to 16MB of program memory and 16MB of data memory
•
True 16/24-bit access to 16/24-bit I/O registers
•
Efficient support for 8-, 16-, and 32-bit arithmetic
•
Configuration change protection of system-critical features
All
XMEGA AU devices use the 8/16-bit AVR CPU. The main function of the CPU is to exe-
AVR
cute the code and perform all calculations. The CPU is able to access memories, perform
calculations, control peripherals, and execute the program in the flash memory. Interrupt han-
dling is described in a separate section,
Controller" on page
101.
In order to maximize performance and parallelism, the AVR CPU uses a Harvard architecture
with separate memories and buses for program and data. Instructions in the program memory
are executed with single-level pipelining. While one instruction is being executed, the next
instruction is pre-fetched from the program memory. This enables instructions to be executed on
every clock cycle. For a summary of all AVR instructions, refer to
page
317. For details of all AVR instructions, refer to http://www.atmel.com/avr.
Figure 3-1.
Block diagram of the AVR CPU architecture.
Atmel AVR XMEGA D
"Interrupts and Programmable Multilevel Interrupt
"Instruction Set Summary" on
5
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