Table of Contents
Advertisement
Boot-Loader Source Code Listing
C.2 Boot-Loader Source Code Listing
**********************************************************************************
* C32BOOT – TMS320C32 BOOT LOADER PROGRAM
*
(C) COPYRIGHT TEXAS INSTRUMENTS INCORPORATED, 1994
*================================================================================*
*
* NOTE:
*
*
1. Following device reset, the program waits for an external interrupt.
*
The interrupt type determines the initial address from which the boot
*
loader will start loading the boot table to the destination memory:
*
*
INTERRUPT PIN
*
*
INT0
*
*
INT1
*
INT2
*
*
INT3
*
*
INT0 and INT3
*
*
INT1 and INT3
*
INT2 and INT3
*
*
If INT3 is asserted together with (INT2 or INT1 or INT0) following reset,
*
that indicates that the boot table is to be read asynchronously from EPROM
*
using pins XF0 and XF1 for handshaking. The handshaking protocol assumes
*
that the data ready signal generated by the host arrives through pin XF1.
*
The data acknowledge signal is output from the C32 on pin XF0.Both signals
*
are active low. The C32 will continuously toggle the IACK signal while
*
waiting for the host to assert data ready signal (pin XF1).
*
*
2. The boot operation involves transfer of one or more source blocks from the
*
boot media to the destination memory. The block structure of the boot table
*
serves the purpose of distributing the source data/program among different
*
memory spaces. Each block is preceded by several 32-bit control words de
*
scribing the block contents to the boot loader program.
*
*
3. When loading from serial port, the boot loader reads the source data/program
*
and writes it to the destination memory. There is only one way to read the
*
serial port. When loading from EPROM, however, there are 4 ways to read and
*
assemble the source contents, depending on the width of boot memory and the
*
size of the program/data being transferred. Because there is a possibility
*
that reads and writes can span the same STRB space the boot loader loads the
*
appropriate STRB control registers before each read and write.
*
*
4. If the boot source is EPROM whose physical width is less than 32 bits, the
*
physical interface of the EPROM device(s) to the processor should be the
*
same as that of the 32-bit interface. (This involves a specific connection
*
to C32's strobe and address signals). The reason for such arrangement is
C-4
BOOT TABLE START ADDRESS
1000h
(STRB0)
810000h
(IOSTRB)
900000h
(STRB1)
80804Ch
(sport0 Rx)
1000h
(STRB0)
810000h
(IOSTRB)
900000h
(STRB1)
(143 words)
March–96
BOOT SOURCE
EPROM,XF0/XF1
ASYNC
EPROM,XF0/XF1
ASYNC
ASYNC
EPROM,XF0/XF1
v.27
EPROM
EPROM
EPROM
SERIAL
Advertisement
Chapters
Table of Contents
