Texas Instruments TMS320C3x User Manual page 263

Example 8–17. Dummy sr2 Read
STI
ADDI3
PC
n
n+1
n+2
n+3
n+4
n+5
n+6
n+7
n+8
R0,*AR6 ; AR6 points to MSTRB space
*AR1,*AR3,R0 ; AR3 points to on-chip RAM ( src 1)
; AR1 points to MSTRB space ( src 2)
H1
H3
Fetch Decode
STI
ADDI3 STI
ADDI3
Two cycles are required for the MSTRB store. Two additional cycles are required
for the dummy MSTRB read of *AR3 (because a read follows a write). One cycle
is required for an actual MSTRB read of *AR3.
Pipeline Operation
Read Execute
STI
— STI
— —
ADDI3 —
— —
ADDI3 —
ADDI3
Pipeline Operation
Clocking Memory Accesses
R0, *AR6 until the
store is complete
2-cycle dummy
load of src 2
actual read of
src 2 and src 1
8-27