Texas Instruments TMS320C3x User Manual page 678

STII
Store Integer, Interlocked
Syntax
Operation
Operands
Opcode
Description
Cycles
Status Bits
Mode Bit
Example
Data memory
8098AEh
13-220
STII src, dst
src dst
Signal end of interlocked operation
src register (R n , 0 n
dst general addressing modes (G):
0 1 direct
1 0 indirect (disp = 0–255, IR0, IR1)
31 24 23
0 0 0 1 0 1 0 1 1
The src register is loaded into the dst memory location. An interlocked opera-
tion is signaled over pins XF0 and XF1. The src and dst operands are assumed
to be signed integers. Refer to Section 7.4, Interlocked Operations , on page
7-13 for detailed information.
1
LUF Unaffected
LV Unaffected
UF Unaffected
N Unaffected
Z Unaffected
V Unaffected
C Unaffected
OVM Operation is not affected by OVM bit value.
STII R1,@98AEh
Before Instruction
R1 00 0000 078D
DP 080
25C
Note:
The STII instruction is not interruptible because it completes when ready is
signaled. See Section 7.4, Interlocked Operations, on page 7-13.
27)
16 15
G
src
R1
DP
8098AEh
8 7
dst
After Instruction
00 0000 078D
080
78D
0