Texas Instruments TMS320C3x User Manual page 703

Syntax
Operation
Operands
Opcode
Description
Cycles
Status Bits
Mode Bit
TSTB src, dst
dst AND src
src general addressing modes (G):
0 0 register (R n , 0
0 1 direct
1 0 indirect (disp = 0–255, IR0, IR1)
1 1 immediate
dst register (R n , 0 n
31 24 23
0 0 0 1 1 0 1 0 0
The bitwise-logical AND of the dst and src operands is formed, but the result
is not loaded in any register. This allows for nondestructive compares. The dst
and src operands are assumed to be unsigned integers.
1
These condition flags are modified for all destination registers (R27 – R0).
LUF Unaffected
LV Unaffected
UF 0
N MSB of the output
Z 1 if a 0 output is generated; 0 otherwise
V 0
C Unaffected
OVM Operation is not affected by OVM bit value.
n 27)
27)
16 15
G
dst
Assembly Language Instructions
TSTB
Test Bit Fields
8 7 0
src
13-245