Texas Instruments TMS320C3x User Manual page 535

Cycles
Status Bits
Mode Bit
Arithmetic right shift:
sign of src2 src2
If the count operand is 0, no shift is performed, and the C bit is set to 0. The
count and dst operands are assumed to be signed integers.
All registers are read at the beginning and loaded at the end of the execute
cycle. If one of the parallel operations (STI) reads from a register and the oper-
ation being performed in parallel (ASH3) writes to the same register, STI ac-
cepts the contents of the register as input before it is modified by the ASH3.
If src2 and dst2 point to the same location, src2 is read before the write to dst2.
1
These condition flags are modified only if the destination register is R7 – R0.
LUF Unaffected
LV 1 if an integer overflow occurs; unchanged otherwise
UF 0
N MSB of the output
Z 1 if a 0 result is generated; 0 otherwise
V 1 if an integer overflow occurs; 0 otherwise
C Set to the value of the last bit shifted out; 0 for a shift count of 0
OVM Operation is not affected by OVM bit value.
Parallel ASH3 and STI
C
Assembly Language Instructions
ASH3||STI
13-77