Texas Instruments TMS320C3x User Manual page 541

Syntax
Operation
Operands
Opcode
Description
Cycles
Status Bits
Mode Bit
Example
BR src
src
PC
src long-immediate addressing mode
31 24 23
0 1 1 0 0 0 0 0
BR performs a PC-relative branch that executes in four cycles, since a pipeline
flush also occurs upon execution of the branch (see Section 8.2, Pipeline Con-
flicts , on page 8-4). An unconditional branch is performed. The src operand is
assumed to be a 24-bit unsigned integer. Note that bit 24 = 0 for a standard
branch.
4
LUF Unaffected
LV Unaffected
UF Unaffected
N Unaffected
Z Unaffected
V Unaffected
C Unaffected
OVM Operation is not affected by OVM bit value.
BR 805Ch
Before Instruction
PC
LUF
LV
UF
N
Z
V
C
Branch Unconditionally (Standard)
16 15
src
PC
0080
LUF
0
LV
0
UF
0
N
0
Z
0
V
0
C
0
Assembly Language Instructions
BR
8 7 0
After Instruction
805C
0
0
0
0
0
0
0
13-83