Bus Timing - Texas Instruments TMS320C3x User Manual

10.10 Bus Timing

10.10.1 STRB0 and STRB1 Bus Cycles
This section discusses functional timing of operations on the external memory
bus. Detailed timing specifications are contained in the TMS320C32 Data
Sheet . The timing of STRB0 and STRB1 bus cycles is identical and discussed
in subsection 10.10.1. The abbreviation STRBx is used in references that per-
tain equally to STRB0 and STRB1. The IOSTRB bus cycles are timed differently
and are discussed in subsection 10.10.2.
All bus cycles comprise integral numbers of H1 clock cycles. One H1 cycle is
defined from one falling edge of H1 to the next falling edge of H1. For full speed
(zero wait-state) accesses on STRB0 and STRB1, writes take two H1 cycles
and reads take one cycle. However, if the read immediately follows a write, the
read takes two cycles. Writes to internal memory take one cycle if no other
accesses to that interface are in progress. The following discussion pertains
to zero wait-state accesses, unless otherwise specified.
The STRBx signal is low for the active portion of both reads and writes (one
H1 cycle). Additionally, before and after the active portions of writes only
(STRBx low), there is a transition of one H1 cycle. During this transition cycle
the following might occur:
-
STRBx is high.
-
If required, R / W changes state on the rising edge of H1.
-
If required, address changes on the rising edge of H1 if the previous H1
cycle performed a write. If the previous H1 cycle performed a read,
address changes on the falling edge of H1.
Figure 10–23 illustrates a zero wait-state read-read-write sequence for STRBx
active. The data is read as late in the cycle as possible to allow for the maximum
access time from address valid. Although external writes take two cycles, writes
to internal memory take one cycle if no other accesses to that interface are in
progress. Similar to typical external interfaces, the R/W signal does not change
until STRB0 and STRB1 are deactivated.
TMS320C32 Enhanced External Memory Interface
Bus Timing
10-39