Example 1
AR0
AR1
LUF
Data memory
809888h
809851h
Example 2
R0
R6
R7
LUF
LV
UF
N
Z
V
C
SUBF3
*AR0
– –
Before Instruction
R4
00 0000 0000
80 9888
80 9851
IR0
80
0
LV
0
UF
0
N
0
Z
0
V
0
C
0
70C8000
733C000
SUBF3
R7,R0,R6
Before Instruction
03 4C20 0000
1.27578125e+01
00 0000 0000
05 7B40 0000
6.281250e+01
0
0
0
0
0
0
0
Note: Cycle Count
See subsection 8.5.2, Data Loads and Stores , on page 8-24 for the effects
of operand ordering on the cycle count.
Subtract Floating-Point Value, 3-Operand
(IR0),*AR1,R4
R4
AR0
AR1
IR0
LUF
LV
UF
809888h
1.4050e+02
809851h
1.79750e+02
R0
R6
R7
LUF
LV
UF
N
Z
V
C
Assembly Language Instructions
After Instruction
05 1D00 0000
3.9250e+01
80 9808
80 9851
80
0
0
0
N
0
Z
0
V
0
C
0
70C8000
1.4050e+02
733C000
1.79750e+02
After Instruction
03 4C20 0000
1.27578125e+01
05 B7C8 0000
–5.00546875e+01
05 7B40 0000
6.281250e+01
0
0
0
0
1
0
0
SUBF3
13-231
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