Texas Instruments TMS320C3x User Manual page 672

STF
Store Floating-Point Value
Syntax
Operation
Operands
Opcode
Description
Cycles
Status Bits
Mode Bit
Example
LUF
Data memory
8098A1h
13-214
STF src, dst
src dst
src register (R n , 0
dst general addressing modes (G):
0 1 direct
1 0 indirect (disp = 0–255, IR0, IR1)
31 24 23
0 0 0 1 0 1 0 0
The src register is loaded into the dst memory location. The src and dst oper-
ands are assumed to be floating-point numbers.
1
LUF Unaffected
LV Unaffected
UF Unaffected
N Unaffected
Z Unaffected
V Unaffected
C Unaffected
OVM Operation is not affected by OVM bit value.
STF R2,@98A1h
Before Instruction
R2
05 2C50 1900
DP
080
0
LV
0
UF
0
N
0
Z
0
V
0
C
0
0
n 7)
16 15
src
0 G
4.30782204e+01
R2
DP
LUF
LV
UF
N
Z
V
C
8098A1h
8 7
dst
After Instruction
05 2C50 1900 4.30782204e+01
080
0
0
0
0
0
0
0
52C5019
4.30782204e+01
0