Texas Instruments TMS320C3x User Manual page 691

Example
R0
R1
R7
AR4
AR5
IR0
IR1
LUF
LV
UF
Data memory
8098B0h
809860h
SUBF3
|| STF
Before Instruction
00 0000 0000
6.28125e+01
05 7B40 0000
1.79750e+02
07 33C0 0000
80 98B8
80 9850
10
8
0
0
0
N
0
Z
0
V
0
C
0
1.4050e+02
70C8000
0
Note: Cycle Count
See subsection 8.5.2, Data Loads and Stores , on page 8-24 for the effects
of operand ordering on the cycle count.
Parallel SUBF3 and STF
R1,*–AR4(IR1),R0
R7,*+AR5(IR0)
After Instruction
R0
06 1B60 0000
R1
05 7B40 0000
R7
07 33C0 0000
AR4
AR5
IR0
IR1
LUF
LV
UF
N
Z
V
C
8098B0h
809860h
Assembly Language Instructions
SUBF3||STF
7.768750e+01
6.28125e+01
1.79750e+02
80 98B8
80 9850
10
8
0
0
0
0
0
0
0
1.4050e+02
70C8000
1.79750e+02
733C000
13-233