Texas Instruments TMS320C3x User Manual page 219

7.6.7 CPU Interrupt Latency
If you wish to make the interrupt service routine interruptible, you can set the
GIE bit to 1 after entering the ISR.
The interrupt acknowledge (IACK) instruction can be used to signal externally that
an interrupt has been serviced. If external memory is specified in the operand,
IACK drives the IACK pin and performs a dummy read. The read is performed
from the address specified by the IACK instruction operand. IACK is typically
placed in the early portion of an ISR. However, depending on your application,
it may be better to place it at the end of the ISR or not at all.
Note the following:
-
Interrupts are disabled during an RPTS and during a delayed branch (until
the three instructions following a delayed branch are completed). Interrupts
are held until after the branch.
-
When an interrupt occurs, instructions currently in the decode and read
phases continue regular execution, unlike an instruction in the fetch
phase:
J
If the interrupt occurs in the first cycle of the fetch of an instruction, the
fetched instruction is discarded (not executed), and the address of
that instruction is pushed to the top of the system stack.
J
If the interrupt occurs after first cycle of the fetch (in the case of a multi-
cycle fetch due to wait states), that instruction is executed, and the
address of the next instruction to be fetched is pushed to the top of
the system stack.
CPU interrupt latency, defined as the time from the acknowledgement of the
interrupt to the execution of the first ISR instruction, is at least eight cycles. This
is explained in Table 7–8 on page 7-36, where the interrupt is treated as an
instruction. It assumed that all of the instructions are single-cycle instructions.
Program Flow Control
Interrupts
7-35