Texas Instruments TMS320C3x User Manual page 660

RND
Round Floating-Point Value
Syntax
Operation
Operands
Opcode
Description
Cycles
Status Bits
Mode Bit
13-202
RND src, dst
rnd( src ) dst
src general addressing modes (G):
0 0 register (R n , 0
0 1 direct
1 0 indirect (disp = 0–255, IR0, IR1)
1 1 immediate
dst register (R n , 0 n
31 24 23
0 0 0 1 0 0 0 1 0
The result of rounding the src operand is loaded into the dst register.The src
operand is rounded to the nearest single-precision floating-point value. If the
src operand is exactly halfway between two single-precision values, it is
rounded to the most positive value.
1
These condition flags are modified only if the destination register is R7 – R0.
LUF 1 if a floating-point underflow occurs; unchanged otherwise
LV 1 if a floating-point overflow occurs; unchanged otherwise
UF 1 if a floating-point underflow occurs or the src operand is 0;
0 otherwise
N 1 if a negative result is generated; 0 otherwise
Z Unaffected
V 1 if a floating-point overflow occurs; 0 otherwise
C Unaffected
OVM Operation is affected by OVM bit value.
n 7)
7)
16 15
G dst
8 7 0
src