Texas Instruments TMS320C3x User Manual page 520

AND
Bitwise-Logical AND
Syntax
Operands
Operands
Opcode
Description
Cycles
Status Bits
Mode Bit
Example
13-62
AND src, dst
dst AND src dst
src general addressing modes (G):
0 0 any CPU register
0 1 direct
1 0 indirect (disp = 0–255, IR0, IR1)
1 1 immediate (not sign extended)
dst any CPU register
31 24 23
0 0 0 0 0 0 1 0 1
The bitwise-logical AND between the dst and src operands is loaded into the
dst register. The dst and src operands are assumed to be unsigned integers.
1
These condition flags are modified only if the destination register is R7 – R0.
LUF Unaffected
LV Unaffected
UF 0
N MSB of the output
Z 1 if a 0 result is generated; 0 otherwise
V 0
C Unaffected
OVM Operation is not affected by OVM bit value.
AND R1,R2
Before Instruction
R1
00 0000 0080
R2
00 0000 0AFF
LUF
LV
UF
N
Z
V
C
16 15
dst
G
0
0
0
0
0
0
1
8 7
src
After Instruction
R1
00 0000 0080
R2
00 0000 0080
LUF
0
LV
0
UF
0
N
0
Z
0
V
0
C
1
0