Texas Instruments TMS320C3x User Manual page 563

Syntax
Operation
Operands
Opcode
Description
Cycles
Status Bits
Mode Bit
FLOAT src2, dst1
src3 , dst2
|| STF
float (src2 ) dst1
|| src3 dst2
src2 indirect ( disp = 0, 1, IR0, IR1)
dst1 register (R n 1, 0
src3 register (R n 2, 0
dst2 register ( disp = 0, 1, IR0, IR1)
This instruction's operands have been augmented in the following devices:
-
'C31 silicon revision 6.0 or greater
-
'C32 silicon revision 2.0 or greater
src2 indirect ( disp = 0, 1, IR0, IR1) or any CPU register
dst1 register (R n 1, 0
src3 register (R n 2, 0
dst2 register ( disp = 0, 1, IR0, IR1)
31 24 23
1 1 0 1 0 1 1 dst 1
An integer-to-floating-point conversion is performed. All registers are read at
the beginning and loaded at the end of the execute cycle. If one of the parallel
operations (STF) reads from a register and the operation being performed in
parallel (FLOAT) writes to the same register, then STF accepts the contents
of the register as input before it is modified by FLOAT.
If src2 and dst2 point to the same location, src2 is read before the write to dst2.
1
These condition flags are modified only if the destination register is R7 – R0.
LUF Unaffected
LV Unaffected
UF 0
N 1 if a negative result is generated; 0 otherwise
Z 1 if a 0 result is generated; 0 otherwise
V 0
C Unaffected
OVM Operation is affected by OVM bit value.
Parallel FLOAT and STF
n 1 7)
n 2 7)
n 1 7)
n 2 7)
16 15
0 0 0 src 3 dst 2
Assembly Language Instructions
FLOAT||STF
8 7 0
src 2
13-105