Texas Instruments TMS320C3x User Manual page 635

Example
R2
R7
AR4
AR5
LUF
LV
UF
Data memory
8098E1h
809804h
NEGF
|| STF
Before Instruction
07 33C0 0000
1.79750e+02
00 0000 0000
80 98E1
80 9803
0
0
0
N
0
Z
0
V
0
C
0
57B400000
6.281250e+01
0
Note: Cycle Count
See subsection 8.5.2, Data Loads and Stores , on page 8-24 for the effects
of operand ordering on the cycle count.
Parallel NEGF and STF
*AR4– – (1),R7
R2,*++AR5(1)
After Instruction
R2
07 33C0 0000
R7
05 84C0 0000
AR4
AR5
LUF
LV
UF
N
Z
V
C
8098E1h
809804h
Assembly Language Instructions
NEGF||STF
1.79750e+02
–6.281250e+01
80 98E0
80 9804
0
0
0
0
0
0
0
57B4000
6.281250e+01
733C000 1.79750e+02
13-177