Texas Instruments TMS320C3x User Manual page 521

Syntax
Operation
Operands
Opcode
Description
Cycles
Status Bits
Mode Bit
AND3 src2, src1, dst
src1 AND src2 dst
src1 3-operand addressing modes (T):
0 0 any CPU register
indirect ( disp = 0, 1, IR0, IR1)
0 1
1 0 any CPU register
indirect ( disp = 0, 1, IR0, IR1)
1 1
src2 3-operand addressing modes (T):
0 0 any CPU register
0 1 any CPU register
1 0 indirect ( disp = 0, 1, IR0, IR1)
1 1 indirect ( disp = 0, 1, IR0, IR1)
31 24 23
0 0 1 0 0 0 0 1 1
The bitwise-logical AND between the src1 and src2 operands is loaded into
the destination register. The src1 , src2 , and dst operands are assumed to be
unsigned integers.
1
These condition flags are modified only if the destination register is R7 – R0.
LUF Unaffected
LV Unaffected
UF 0
N MSB of the output
Z 1 if a 0 result is generated; 0 otherwise
V 0
C Unaffected
OVM Operation is not affected by OVM bit value.
Bitwise-Logical AND, 3-Operand
16 15
dst
T
Assembly Language Instructions
8 7
src 1 src 2
AND3
0
13-63