Combined Effect Of The Ce And Cf Bits - Texas Instruments TMS320C3x User Manual

Table 4–1. Combined Effect of the CE and CF Bits
Example 4–1. Pipeline Effects of Modifying the Cache Control Bits
Cycle
n
n+1
n+2
n+3
Instructions may
be fetched before
n+4
cache cleared.
n+5
n+6
n+7
n+8
CE
0
0
1
1
When the CE or CF bits of the CPU status register are modified, the following
four instructions may or may not be fetched from the cache or external memory
(see Example 4–1).
When the CC bit of the CPU status register is modified, the following five instruc-
tions may or may not be fetched from the cache before the cache is cleared (see
Example 4–1).
Fetch
LDI 1000h, ST
LDI 1h, R1 LDI 1000h, ST
LDI 2h, R2
LDI 3h, R3
LDI 4h, R4
LDI 5h, R5
CF
0
1
0
1
Pipeline Operation
Decode
LDI 1h, R1 LDI 1000h, ST
LDI 2h, R2 LDI 1h, R1
LDI 3h, R3 LDI 2h, R2
LDI 4h, R4 LDI 3h, R3
LDI 5h, R5 LDI 4h, R4
LDI 5h, R5
Memory and the Instruction Cache
Instruction Cache
Effect
Cache not enabled
Cache not enabled
Cache enabled and not frozen
Cache enabled and frozen
Read Execute
Instructions may
be fetched before
cache is enabled
or frozen.
Cache cleared
LDI 1000h, ST
LDI 1h, R1
LDI 2h, R2
LDI 3h, R3
LDI 4h, R4
LDI 5h, R5
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