Texas Instruments TMS320C3x User Manual page 103

4.3.2 Instruction-Cache Algorithm
When the 'C3x requests an instruction word from external memory, one of two
possible actions occurs: a cache hit or a cache miss .
-
Cache Hit. The cache contains the requested instruction, and the following
actions occur:
J
The instruction word is read from the cache.
J
The number of the segment containing the word is removed from the
LRU stack and pushed to the top of the LRU stack (if it is not already at
the top), thus moving the other segment number to the bottom of the
stack.
-
Cache Miss. The cache does not contain the instruction. There are two
types of cache misses:
J
Subsegment miss. The segment address register matches the instruc-
tion address, but the relevant P flag is not set. The following actions
occur in parallel:
H
The instruction word is read from memory and copied into the cache.
H
The number of the segment containing the word is removed from
the LRU stack and pushed to the top of the LRU stack (if it is not
already at the top), thus moving the other segment number to the
bottom of the stack.
H
The relevant P flag is set.
J
Segment miss. Neither of the segment addresses matches the instruc-
tion address. The following actions occur in parallel:
H
The LRU segment is selected for replacement. The P flags for all
32 words are cleared.
H
The SSA register for the selected segment is loaded with the
19 MSBs of the address of the requested instruction word.
H
The instruction word is fetched and copied into the cache. It goes
into the appropriate word of the LRU segment. The P flag for that
word is set to 1.
H
The number of the segment containing the instruction word is
removed from the LRU stack and pushed to the top of the LRU
stack, thus moving the other segment number to the bottom of
the stack.
Memory and the Instruction Cache
Instruction Cache
4-21