Texas Instruments TMS320C3x User Manual page 693

Syntax
Operation
Operands
Opcode
Description
Cycles
Status Bits
Mode Bit
SUBI3 src2, src1, dst
src1 – src2 dst
src1 3-operand addressing modes (T):
register (R n 1, 0
0 0
0 1 indirect ( disp = 0, 1, IR0, IR1)
register (R n 1, 0
1 0
1 1 indirect ( disp = 0, 1, IR0, IR1)
src2 3-operand addressing modes (T):
0 0 register (R n 2, 0
0 1 register (R n 2, 0
1 0 indirect ( disp = 0, 1, IR0, IR1)
1 1 indirect ( disp = 0, 1, IR0, IR1)
dst register (R n , 0 n
31 24 23
0 0 1 0 0 1 1 1 0
The difference between the src1 operand and the src2 operand is loaded into
the dst register. The src1 , src2 , and dst operands are assumed to be signed
integers.
1
These condition flags are modified only if the destination register is R7 – R0.
LUF Unaffected
LV 1 if an integer overflow occurs; unchanged otherwise
UF 0
N 1 if a negative result is generated; 0 otherwise
Z 1 if a 0 result is generated; 0 otherwise
V 1 if an integer overflow occurs; 0 otherwise
C 1 if a borrow occurs; 0 otherwise
OVM Operation is affected by OVM bit value.
Subtract Integer, 3-Operand
n 1
27)
n 1
27)
n 2 27)
n 2 27)
27)
16 15
T
dst
Assembly Language Instructions
8 7
src 1 src 2
SUBI3
0
13-235