Texas Instruments TMS320C3x User Manual page 622

MPYI3||ADDI3
Parallel MPYI3 and ADDI3
13-164
This instruction's operands have been augmented in the following
devices:
-
'C31 silicon version 6.0 or greater
-
'C32 silicon version 2.0 or greater
srcA , srcB , srcC , srcD can be one of the following combinations:
Register
v v
R n
(0 7)
2
2
2
dst1 register ( d1 ):
0 = R0
1 = R1
dst2 register ( d2 ):
0 = R2
1 = R3
src1 register (R n , 0
src2 register (R n , 0
src3 indirect ( disp = 0, 1, IR0, IR1) or any CPU register
src4 indirect ( disp = 0, 1, IR0, IR1) or any CPU register
P parallel addressing modes (0
Version 4.7 or earlier of TMS320 floating-point code-generation tools
P
00
01
10
11
Version 5.0 or later
P
00
01
10
11
Indirect
( disp = 0,1,IR0,IR1)
2
1
–
n 7)
n
7)
srcA srcB srcD
src4 src3, src1 + src2
src3 src1, src4 + src2
src1 src2, src4 + src4
src3 src1, src2 + src4
srcA srcB srcD
src3 src4, src1 + src2
src3 src1, src4 + src2
src1 src2, src3 + src4
src3 src1, src2 + src4
Any CPU Register
–
1
2
P 3)
srcC
srcC