Texas Instruments TMS320C3x User Manual page 448

Figure 12–47. DMA Timing When Destination is On Chip
Cycles (H1)
Source on chip
Destination on chip
Source STRB, STRB0, STRB1, MSTRB bus Source STRB STRB0 STRB1 MSTRB bus
Destination on chip
Source IOSTRB bus Source IOSTRB bus
Destination on chip
Legend:
T = Number of transfers
C r = Source-read wait states
C w = Destination-write wait states
R = Single-cycle reads
1 2 3 4 5 6
R 1 R 2 R 3
W 1 W 2 W 3
R 1 R 1 R 1 I R 2
C r
W 1
R 1 R 1 R 1 R 1 I
C r
W 1
W = Single-cycle writes
R n = Multicycle reads
W n = Multicycle writes
I = Internal register cycle
7 8 9 10 11 12 13 14
R 4 R 5 R 6 R 7
W 4 W 5 W 6 W 7
R 2 R 2 I R 3 R 3 R 3 I
C r C r
W 2
R 2 R 2 R 2 R 2 I R 3 R 3
C r
W 2
15 16 17 18 Rate
R 8
(1 + 1) T (1 + 1) T
(2 + C r +1) T
W 3
R 3 R 3 I
C r (3 + C r + 1) T
W 3