Texas Instruments TMS320C3x User Manual page 577

Syntax
Operation
Operands
Opcode
Description
Cycles
Status Bits
Mode Bit
LDF src2, dst2
LDF src1, dst1
||
src2 dst2
|| src1 dst1
src1 indirect ( disp = 0, 1, IR0, IR1)
dst1 register (R n 1, 0
src2 indirect ( disp = 0, 1, IR0, IR1)
dst2 register (R n 2, 0
This instruction's operands have been augmented on the following devices:
-
'C31 silicon revision 6.0 or greater
-
'C32 silicon revision 2.0 or greater
src1 indirect ( disp = 0, 1, IR0, IR1)
dst1 register (R n 1, 0
src2 indirect ( disp = 0, 1, IR0, IR1) or any CPU register
dst2 register (R n 2, 0
31 24 23
1 1 0 0 0 1 0 dst 2
Two floating-point loads are performed in parallel. If the LDFs load the same
register, the assembler issues a warning. The result is that of LDF src2, dst2.
1
LUF Unaffected
LV Unaffected
UF Unaffected
N Unaffected
Z Unaffected
V Unaffected
C Unaffected
OVM Operation is not affected by OVM bit value.
Parallel LDF and LDF
n 1 7)
n 2
7)
n 1 7)
n 2 7)
16 15
dst 1 0 0 0 src 1
Assembly Language Instructions
LDF||LDF
8 7 0
src 2
13-119