Texas Instruments TMS320C3x User Manual page 487

Figure 13–6. Status Register
13 16 15
PRGW
xx
status
('C32 only) ('C32 only)
R
Note: xx = reserved bit, read as 0
R = read, W = write
LUF
LV
UF
N
Z
V
C
14 13 12 11
INT
GIE CC CE CF
config
R/W R/W R/W R/W R/W
Latched floating-point underflow condition flag. LUF is set whenever UF
(floating-point underflow flag) is set. LUF can be cleared only by a processor
reset or by modifying it in the status register (ST).
Latched overflow conditionfFlag. LV is set whenever V (overflow condition
flag) is set. Otherwise, it is unchanged. LV can be cleared only by a processor
reset or by modifying it in the status register (ST).
Floating-point underflow conditionflag. A floating-point underflow occurs
whenever the exponent of the result is less than or equal to –128. If a floating-
point underflow occurs, UF is set, and the output value is set to 0. UF is
cleared if a floating-point underflow does not occur.
Negative condition flag. Logical operations assign N the state of the MSB
of the output value. For logical operations, V is set to the state of the MSB.
For integer and floating-point operations, N is set if the result is negative and
cleared otherwise. A 0 is positive.
Zero condition flag. For logical, integer, and floating-point operations, Z is
set if the output is 0 and cleared otherwise.
Overflow condition flag. For integer operations, V is set if the result does
not fit into the format specified for the destination (that is, –2
32
– 1). Otherwise, V is cleared. For floating-point operations, V is set if the
exponent of the result is greater than 127; otherwise,V is cleared. Logical
operations always clear V.
Carry flag. When an integer addition is performed, C is set if a carry occurs
out of the bit corresponding to the MSB of the output. When an integer
subtraction is performed, C is set if a borrow occurs into the bit corresponding
to the MSB of the output. Otherwise, for integer operations, C is cleared. The
carry flag is unaffected by floating-point and logical operations. For shift
instructions, this flag is set to the last bit shifted out; for a 0 shift count , this
is set to 0.
10 9 8 7
xx RM OVM LUF
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Assembly Language Instructions
Condition Codes and Flags
6 5 4 3 2
LV UF N Z
32
1 0
V C
result 2
13-29