Table of Contents
Advertisement
Figure 12–49. DMA Timing When Destination is an IOSTRB Bus
Cycles (H1)
1
2
Source on chip
R 1
R 2
W 1
W 1
Destination IOSTRB
Destination IOSTRB
('C30 only)
R 1
R 1
R 1
Source STRB bus
C r
Destination IOSTRB bus
Destination IOSTRB bus
Source STRB0, STRB1,
R 1
R 1
R 1
MSTRB bus
C r
Destination IOSTRB
Legend:
T
= Number of transfers
Cr
= Source-read wait states
Cw = Destination-write wait states
R
= Single-cycle reads
† Write followed by read incurs in one extra cycle.
3
4
5
6
7
8
9
R 3
W 1
W 1
W 2
W 2
W 2
W 2
C w
C w
I
R 2
R 2
R 2
I
C r
W 1
W 1
W 1
W 1
C w
I
R 2
W 1
W 1
W 1
W 1
C w
W
= Single-cycle writes
R n
= Multicycle reads
W n
= Multicycle writes
I
= Internal register cycle
10
11
12
13
14
15
16
R 4
R 5
W 3
W 3
W 3
W 3
W 4
W 4
W 4
C w
C w
R 3
R 3
R 3
I
C r
W 2
W 2
W 2
W 2
W 3
W 3
C w
R 2
R 2
I
C r
W 2
W 2
W 2
W 2
C w
17
18
Rate
W 4
1 + (2 + C w ) T
1 + (2 + C w ) T
(2 + C r + 2 + C w ) + (2 + C w +
max (1, C r – C w + 1)) ( T – 1)
max (1, C r – C w + 1)) ( T – 1)
W 3
W 3
C w
{
{
(2 + C r + 2 + C w ) T + ( T –1)
(2
C
2
C ) T
( T 1)
Advertisement
Chapters
Table of Contents
Need help?
Do you have a question about the TMS320C3x and is the answer not in the manual?