Texas Instruments TMS320C3x User Manual page 711

Status Bits
Mode Bit
Example
Data memory
80987Eh
8098ACh
These condition flags are modified only if the destination register is R7 – R0.
LUF Unaffected
LV Unaffected
UF 0
N MSB of the output
Z 1 if a 0 output is generated; 0 otherwise
V 0
C Unaffected
OVM Operation is not affected by OVM bit value.
XOR3
|| STI
Before Instruction
R3
00 0000 0085
R6
00 0000 00DC
AR1
80 987E
AR2
80 98B4
IR0
LUF
LV
UF
N
Z
V
C
85
Note: Cycle Count
See subsection 8.5.2, Data Loads and Stores , on page 8-24 for the effects
of operand ordering on the cycle count.
Parallel XOR3 and STI
*AR1++,R3,R3
R6,*–AR2(IR0)
R3
220 R6
AR1
AR2
IR0
8
LUF
0
LV
0
UF
0
N
0
Z
0
V
0
C
0
80987Eh
8098ACh
0
Assembly Language Instructions
XOR3||STI
After Instruction
00 0000 0000
00 0000 00DC
220
80 987F
80 98B4
8
0
0
0
0
0
0
0
85
0DC
220
13-253