Tms320C32 Dma Internal Priority Schemes - Texas Instruments TMS320C3x User Manual

DMA Controller

12.3.5 TMS320C32 DMA Internal Priority Schemes

12.3.5.1 Fixed Priority Scheme
12-62
Table 12–7. CPU/DMA Interrupt-Enable Register Bits (Continued)
Reset
Abbreviation
Value
ETINT0 (DMA) 0
ETINT1 (DMA) 0
ETINT0 (DMA0) 0
ETINT1 (DMA0) 0
ETINT0 (DMA1) 0
ETINT1 (DMA1) 0
EDINT (DMA) 0
EDINT1 (DMA0) 0
EDINT0 (DMA1) 0
EINT0 (DMA1) 0
EINT1 (DMA1) 0
EINT2 (DMA1) 0
EINT3 (DMA1) 0
Because all accesses made by the two DMA channels take place over one
common internal DMA data and address bus, a priority scheme for bus arbitra-
tion is required. Within the DMA controller, two priority schemes are used to
designate which channel is serviced next:
-
A fixed priority scheme with channel 0 always having the highest priority
and channel 1 the lowest
-
A rotating priority scheme that places the most recently serviced channel
at the bottom of the priority list (default setup after reset)
This scheme provides a fixed (unchanging) priority for each channel as follows:
To select fixed priority, set the PRIORITY MODE bit (bit 14) of channel 0's
DMA-channel control register to 1.
Description
DMA timer0 interrupt enable ('C30 and 'C31)
DMA timer1 interrupt enable ('C30 and 'C31 only)
DMA0 timer1 interrupt enable ('C32 only)
DMA0 timer1 interrupt enable ('C32 only)
DMA1 timer0 interrupt enable ('C32 only)
DMA1 timer1 interrupt enable ('C32 only)
DMA controller interrupt enable ('C30 and 'C31)
DMA0-DMA1 controller interrupt enable ('C32 only)
DMA1-DMA0 controller interrupt enable ('C32 only)
DMA1 external interrupt 0 enable ('C32 only)
DMA1 external interrupt 1 enable ('C32 only)
DMA1 external interrupt 2 enable ('C32 only)
DMA1 external interrupt 2 enable ('C32 only)
Priority Channel
Highest 0
Lowest 1