Texas Instruments TMS320C3x User Manual page 434

Table 12–6. DMA Global-Control Register Bits Summary (Continued)
Reset
Abbreviation
Value
INCSRC 0
DECSRC 0
INCDST 0
DECDST 0
SYNC 0
TC 0
TCINT 0
Name
DMA source address
increment mode
DMA source address
decrement mode
DMA destination
address increment
mode
DMA destination
address decrement
mode
DMA synchronization
mode
DMA transfer mode
DMA transfer counter
interrupt mode
Description
If INCSRC = 1, the source address is incremented after every
read.
If DECSRC = 1, the source address is decremented after
every read.
If INCSRC = DECSRC, the source address is not modified
after a read.
If INCDST = 1, the destination address is incremented after
every write.
If DECDST = 1, the destination address is decremented after
every write.
If INCDST = DECDST, the destination address is not modified
after a write.
Determines the timing synchronization between the events
initiating the source and destination transfers.
The following table summarizes the SYNC bits and DMA
synchronization.
Bit 9 Bit 8 Function
0 0 No synchronization. Enabled interrupts
are ignored (reset value).
0 1 Source synchronization. A read is per-
formed when an enabled interrupt occurs.
1 0 Destination synchronization. A write is per-
formed when an enabled interrupt occurs.
1 1 Source and destination synchronization. A
read is performed when an enabled interrupt
occurs. A write is then performed when the
next enabled interrupt occurs.
Affects the operation of the transfer counter.
If TC = 0, transfers are not terminated when the transfer
counter becomes 0.
If TC = 1, transfers are terminated when the transfer
counter becomes 0.
If TCINT = 1, the DMA interrupt is set when the transfer
counter makes a transition to 0.
If TCINT = 0, the DMA interrupt is not set when the transfer
counter makes a transition to 0.
DMA Controller
Peripherals 12-55