Texas Instruments TMS320C3x User Manual page 602

LSH3||STI
Parallel LSH3 and STI
Example 2
13-144
LSH3 R7,*AR2
|| STI R0,*+AR0(1)
Before Instruction
R0
00 0000 012C
R2
00 0000 0000
R7
00 FFFF FFF4
AR0
AR2
LUF
LV
UF
N
Z
V
C
Data memory
809863h
8098B8h
Note: Cycle Count
See Section 8.5.2, Data Loads and Stores , on page 8-24 for the effects of
operand ordering on the cycle count.
– – (1),R2
300
–12
80 98B7
80 9863
0
0
0
0
0
0
0
2C000000
0
After Instruction
R0
00 0000 012C
R2
00 0002 C000
R7
00 FFFF FFF4
AR0
80 98B7
AR2
80 9862
LUF
LV
UF
N
Z
V
C
809863h
2C000000
8098B8h
12C
300
–12
0
0
0
0
0
0
0
300