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ADDRESS 0109:
The first byte, which
was read and set into the R-register is
transferred to the G-register by the
expression R->G.
The G-register is
interrogated later in the program to
determine the Op code.
The data move-
ment from the R-register to the G-
register is through ALU.
The output of
ALU, if you will recall, feeds the Z
bus.
On line C, the expression, HZ->S4,
brings up control lines that check the
four high bits of the Z bus for zero.
Position 4 of the
S~register
is set to a
one if the high bits are zero.
Since
the data on the Z bus is:
1
A
0001
1010
the first byte of the instruction, S4 is
not set.
The four high bits are 0001.
The S4 bit is interrogated in a Branch
and Link routine and has no bearing on
our example.
Because core readout is destructive
readout, the information in the R-
register is returned to core
by
the
statement, WRITE.
A 1,0 branch is forced by the R line
expression.
If you look at the next
address OlOE, and convert the E to
binary, 1110, you·ll notice that the two
low-order bits are 10.
ADDRESS OlOE:
Because the Op code is
stored in the G-register, the next byte
of the instruction is read from core by
the expression IJ->MN MS.
This is the
byte that contains the addresses of the
two general purpose registers.
Once the MN registers have been set,
the J-register is again updated by the
expression
J
+
0
+
l->JC.
Notice that a
new element has been added to the arith-
metic statement.
The C to the right of
the arrow allows a carryout, as a result
of adding a one to the data in J. to set
the third position of the S register.
If no carryout results, the S3 position
is set to zero.
This is necessary
because, should a carryout result, the
I-register address portion must also be
updated.
Assume at this point there is
a carryout, that S3 is,set to a one, and
let's see when and how this is handled
by the micro program.
The C line of this ROS word causes
the control lines to set SO to zero.
The 0 position of the S-register is a
control for true or complement add when
the arithmetic operation is undetermined
(t).
If SO is zero, the arithmetic
operation is a true add.
If SO is a "
the operation is complement.
The G-register positions 0 and 1 are
interrogated by the expression GO, Gl.
See Figure 3-22.
The data in the G-
register is
1
A
0001
1010
testing these positions tells us that
our
Op
code must be in RR format.
RX Op
codes begin with
01,
RS with
10,
and SS
with 11.
Because GO and G1 are both zero, a 00
branch is taken to address
0118.
ADDRESS 0118:
The data in the R-
register is again returned to core by
the WRITE expression.
The arithmetic expression IJl.->D
will OR the data in the L- and R-
registers and transfer the resultant
answer to the D-register.
The symbol
for the OR function is the omega.
The
L-register is always zero on entering
I-phase except for the EXECUTE Op code.
Since the L-register is zero and the
R-register contains the second byte of
the instruction, the D register is set
01110101.
The low-order four bits of the Z bus
are checked for a zero condition by the
expression LZ->S5.
S5 is set to a 1 if
the data on the low portion of the Z bus
is zero.
Because the data on the low
portion of the Z bus is 0101, S5 is not
set to one.
A test is made on other positions of
the G-register to further decode the
instruction.
Looking at Figure 3-22, we
see that by checking G2 and G3 our Op
code must now be in the right-hand
column under FIXED POINT.
The G2 and G3
positions set x6 and X7 to 01, which are
the low-order bits of the next address
to be executed, 011C.
Let's pause for a moment to check the
data in the registers.
The D-register
3-27
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