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6.
P
7.
Clock Start Control, E-cycle Stop
Sample, and Clock Start latches
8.
After T4 time
9.
P2 and P3 -
10.
False
ANSWERS -- ARITHMETIC OPERATION
1.
The A and the B-registers
2.
8
3.
Micro-programming
4.
Add, and, or, exclusive or
5.
Higb, low, straight, cross, cross
higb, cross low.
6.
High, low, straight
7.
Excess six, decimal add
8.
No carry out of the high order
position of a group.
9.
False
10.
3,
S
11.
Carry latch, . carry-in latch
ANSWERS -- REGISTERS
1.
Storage
)
2.
ROS
3.
polarity hold, AOI
4.
True
5.
False
ANSWERS -- CORE STORAGE
1.
Three, an X-line, a Y-line, and an
Inhibit-Sense Line.
2.
X, Y, MN-Regs.
3.
The base of the decode switch is
conditioned by the
~-register
4, 5,
6, and 7 bits.
The emitter of the
6-22
decode switch is conditioned by the
N-register 2, and 3 bits.
4.
The base of the decode switch is
conditioned by the M-register
6
and
7
bits plus the N-register
0
and 1
bits.
The emitter of the decode
switch is conditioned by the M-
register 3, 4, and 5 bits.
5.
Coincidence of current flow in an
X-band and Y-line, the flipping of
a core, strobing of the pulse.
6.
2 sets of X-lines, 1 set of Y-lines
3
phase reversal planes.
7.
R-reg.
8.
When a core flips from the logical
1 state to the logical 0 state.
9.
Strobe pulse
10.
Not flow.
11.
To reverse the direction of current
flow in the Y-lines of
corresponding planes in alternate
8X
arrays.
(i.e., if Y-current is
flowing from top to bottom is left
to through the 1-bit plane of the
first
8X
array, it will be flowing
from bottom to top through the
l-bit plane of the second
8R
array.
12.
Of·the lower or upper 32R clock.
13.
M 0 bit, on
14.
16
gate decode switches
15.
16
gate decode switches
16.
Emitter and base conditioned to
conduct.
17.
To cause current to flow opposite
the X-lines to prevent the core
from flipping if the bit is not
desired in storage.
18.
The maintenance manual.
19.
X-lines, Y-lines.
ANSWERS-- ROS CONCEPTS
1.
line driver
2.
SAL
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