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ADDRESS 0122:
The expression UV->MN LS
addresses core to read out the first
byte from general purpose register 5.
The data read out is 01011101 (93).
Local storage. rather than main storage,
is specified by the LS portion of the
expression.
The arithmetic S-KH->S sets to zero
all positions of the 5 register except
51.
To see how this is possible, let's
assume for the moment that, in addition
to the 53 position that has been set,
the 51 position is also set to a 1.
The
• in the expression is the symbol for
the AND function.
The A source data
(01010000) is set from the S-register.
KH brings up control pOints to gate the
high (H) portion of the B register data
to ALU.
Remember, the B register is set
by the CK ROS control field.
S-reg. position
01234567
5 reg Set
01010000=A source data
01000000 =B source data
------------------------------------
Result of AND
01000000
Therefore, the result of the AND
function is to allow 51 to remain set
and to reset the other positions of the
S-register.
The last two bits of the Op code are
checked by the expression G6 G7.
These
last positions are set 1,0 and a branch
is executed to address 016E.
The micro
program has .fully decoded the G-register
data to determine that the Op code must
be a Fixed-Point Binary A.dd in RR
Format.
While this was being done, we
have been setting up register addresses
and even read our first byte of data
from register 5.
ADDRESS 016E:
The first byte of data
from general purpose register
5
must be
stored before reading any data from
register 7.
This is done by the expres-
sion R->D.
The information in the D-
register is no longer needed and it is
replaced
by
the data from register 5.
The first byte of data is regenerated by
the expression WRITE.
The expression on the top R line is
K->W.
The W-register, if you will
remember, controls the high-order poSi-
tions of the ROAR address.
The CK con-
trol field (K) value sets the W-register
to the value shown on the E line of this
block.
To explain why, let's look at
the branch line.
On
the lower R line, an unconditional
1,1 branch is executed to address 03A3.
All the ROS words until now have been at
addresses 01XX.
When the second high-
order position of the ROS word address
changes value, the W-register must be
set to a new value.
Since we are at
address
01XX and must step to
03XX,
the expression K->W is used.
Notice,
the E line specifies the binary value of
3.
ADDRESS 03A3:
The first byte of data
from register 7 is read from core
by
the
expression T->N
LS.
The N-register is
set by the data in the T-register.
LS
defines the core area addressed as local
storage.
As this is being done, the expression
v-o->v causes the value of one to
be
subtracted from the V-register.
The
V-Register contains the address of byte
3 and must
be
changed before the next
byte of data for this register is read.
Let's see how ONE is subtracted by the
expression v-o.
Reg 7
Byte 3
V-register data
= 0111
0011
minus 0
+
=
1111
1111
Reg 7
Byte
2
V-register result
=
0111
0010
As you can see, some arithmetic
statements should be worked out in
detail less the wrong impression be
assumed from just the reading of the
statement.
A 0,0 branch to address 03A4 is taken
because 57 is still a zero.
ADDRESS 03A4:
The first byte of data
from register 5 and register 7 is added
together by the expression RtD+C->RC The
C to the left of the arrow is a condi-
tional carry insert.
If the third posi-
tion of the S-register is set to a
1,
then a carry is inserted.
The C to the
right of the arrow allows a carry out
that may result from the addition of the
Rand D data to set 53.
The arithmetic
operation, t, is determined to be an add
because the SO pOSition of the
5
reg-
ister is not set to a
1.
Had it been
the Subtract Op code, SO would have been
3-31
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