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set to a 1 at ROS word address 016F
figure location
J).
SO, if you recall,
is the true or complement controlposi-
tion of the S-register.
We know that it
is a binary add rather than a decimal
add because binary is specified on the E
line of the CAS block.
The result of the addition is:
R
=
+01011101
Reg 1 byte
3 =
+10011001
----~
.....
------~----~--------
R-register result
=
11110110
The expression ANSNZ->S2 sets S2 to a
one because the Z bus has on it the data
11110110.
ANSNZ means Answer Non Zero.
82
is tested further in the program to
determine whether our answer is plus,
minus, or zero.
Since positions 5 and 6 of the S-
register are zero, a 0,0 branch is
executed to address 0100.
Because we
are again changing the second high digit
of our address, the expression K->W is
used.
This time the value of K is
1
as
shown on the Eline.
A.DDRESS 0100:
The sum of the first
byte from each register is regenerated
(WRITE).
The data in byte 3 of register
1 is now 11110110.
An unconditional 1,0
branch is executed to address 01CE at
location E4.
Again, let's pause for a moment to
review where the data is and the
addresses in our registers.
1.
The V-register contains Reg
5
Byte
2
0101
0010.
2.
The T-register contains Reg 1 Byte 3
0111
0011
3.
Register
7
byte 3 data is 1111 0110
or
246
4.
The Sl and S2 positions of the S
register are set to one.
5.
The G-register contains 0001
1010
ADDRESS 01CE:
The second byte of data
from register 5 is read by the expres-
sion, UV->MN M/LS.
M/LS can be either
main core (M) or local storage (LS).
This portion of the expression further
checks the G-register.
Since G-register
determines that our Op code is in RR
format, only the control lines for local
storage are brought up.
The second byte
3-32
of data read from register 5 is
000000000.
While register 5, byte 2 is read,
there is no reason why the address of
the next byte from register 7 cannot be
set up.
This is done
by
T-O->T, which
subtracts one from the data in the
'1-
register.
The resultant answer in the
'I-register is
Reg
7
Byte
2
0111
0010.
The expression LZ->S5 does not set S5
to a one at this time.
LZ is a check
for zero on the four lower bits on the
Z
bus as a result of the arithmetic
statement T-O->T.
As you can see, these
four lower bits will not be
zero until the last address of register
1 is obtained,
Reg
7
Byte 0
0111
0000.
A 0,
1
branch is taken to address
01Cl.
ADDRESS 01Cl:
The byte of data just
read is regenerated (WRITE).
This data
is also stored in the D-register, R->C.
The D-register now contains 000000000,
or byte
2
o.f register 1.
A 1,1 branch is executed to
address 03A3.
Position 3 of the G-
register is a 1 because our Op code is
still stored there.
ADDRESS 03A3:
We have been in this block before.
You
should begin to realize that we are in a
small loop and will exit from it once
all four bytes of data from the two
registers have been added together.
The second byte from register 1 is
read, (T->N LS) •
The V-register address is changed to
Reg 1
Byte 1
0111
0001.
A 0, 0 branch is executed to address
03A4 because S1 is still zero.
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