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c.
Turn on RD---OIO (MM302). This is
the X decode switch for the source
side of the X-line.
X RD O-SK WR S-16K Source
RDI O-SK WR S-16KA
(not)
N
Reg S Bit
(not) N Reg
7
Bit
d.
Turn on RDOlO--- (MM322) .
This is
the sink side of the X line.
X RD O-SK WRS-16K Sink
RDI O-SK WR S-16KB
(not) N Reg 2 Bit
N Reg 3 Bit
(not) N Reg 4 Bit
6.
Develop the sense amplifier gate so the
appropriate sense windings are gated to
their respective sense amplifiers.
The
gate for this address is SA gate O-SKA
(MM692) .
Not M Reg 1 Bit Cont
(not) M Reg 2 Bit
(not) N Reg 7 Bit
7.
Amplify and gate the sense pulses to
the sense amplifier detector latches
(MMS12 through MMS92) .
SA Gate O-SKA
SA In
Bit O-SK
Strobe 0-16K (from clock)
S.
After the SA detector latches are set,
the storage unit signals the 2030 CPU
that the read data is ready (MM002).
Data Ready (from clock)
9.
Without changing the address in the M-
and N-registers, the 2030 CPU requests
a storage write cycle and starts the
storage clock (MM122).
10.
2-S4
Write Call
Set up the storage clock for a write
cycle by turning on the write set latch
(MM1l3) .
Write Call
Go (not M Reg 0 Bit).
11.
For the write cycle, it is necessary
to select and drive the same X and Y
drive lines as were driven on the
read cycle.
However, now they are
driven with current in the opposite
direction.
Consider the Y-line first.
For this, it is necessary to turn on
two control drivers (one for each end
of the Y-line), two address decode
switches (one for each end of the Y-
line), S two address gates (one for
each decode switch), and the Y-write
current source.
12.
a.
Turn on the Y control-drivers,
Write Control 0-32KB and Write
Control 0-32KA (MM222).
Write B (from clock)
Use Main Storage
b.
Turn on the Y-write current
source and sink (MM2S2).
Y Source Write (from clock)
Go (not M Reg 0 Bit)
c.
Turn on the Wr-O--OIO write ad-
dress decode driver (MM402).
This
includes the address gate, and is
on the sink end of the X line.
(not) M Reg 7 Bit Ctrl
(not) M Reg 4 Bit Ctrl
N Reg 0 Bit
Y Wr Current Sink
Write Control 0-32KA
d.
Turn on the WR OOOl---write ad-
dress decode driver (MM442).
This
includes the address gate, and is
on the source end of the X-line.
M Reg Not 3 and Not 4 Bits
(not) M Reg S Bit
M Reg 6 Bit
Write Control 0-32KB
Y Wr Current Source
Select and drive the same X-line in
the opposite direction.
This requires
two control drivers (one for each end
of the X-line), two address decode
switches (one for each end of the X-
line) and two address gates (one for
each decode switch), and the X-write
current source.
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