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Control
Section
Fixed
Point
Operatior
Sixteen
General
Registers
Main
Storage
Figure 1-14.
16 General Registers
ALU
These registers are numbered 0-15 and
are addressed in an instruction by a
4-bit binary address field.
Being a word in length, a general
register can easily contain a half word
data field.
As can be seen in Figure 1-15, the
bits of a general register are numbered
left to right starting with the number
O.
Also we can see that a half word
operand is placed in the low-order half
(bits 16-31) of a General Register.
BitO - - - 1 5 1 6 - - 3 1
I
Half Word
I
.
Operand
.
GENERAL REGISTER
Figure 1-15.
General Register
None of the General Registers 0-15
can contain a double word.
For those
operations that use a double word oper-
and, such as fixed length divide, a pair
of adjacent registers are used.
In
these cases, an even-odd pair of reg-
isters (such as 0-1 or 6-7) are used,
and the even register is addressed.
In this case bits 0-63 of the double
word would be in the registers as shown
in Figure 1-16.
0
31
0
31
1
0
DOUbl~
Word
63
1
Reg 12
Reg 13
Figure 1-16.
Using Two General
Registers
Fixed-length operands in main storage
must be on integral boundaries or a
program check will occur indicating a
specification exception.
The general registers are also used
for purposes other than accumulating.
For example, a general purpose register
can be used as an index register.
Indexing is a form of indirect address-
ing.
An increment contained in an index
register is added to the data address in
the instruction to form an effective
main storage address.
Neither the index
register nor the instruction in storage
is changed by indexing_
1-15
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