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The Set System Mask instruction is a
privileged instruction.
This is because
the system mask affects I/O interrupts.
The System/360 is designed to have the
supervisor handle all
1/0
operations.
For this reason, the Set System Mask
instruction and the four
1/0
instruc-
tions are privileged operations.
The
Set System Mask instruction is of the SI
format.
r--------~----~---T----~-'
lOp Code
I
12
IB1
I
D1
I
________
~
____
~
____
~
______ J
This Set System Mask instruction is
similar to Load PSW instruction in that
the
1/0
field is ignored.
r----~--~~----,
I
80
I
12
I
B1
I
D1
I
l ____
~
____
A_ ___
~
____
J
t
t
Set System
I
Mask Op
I
Code in Hex
I
Effective address
of byte that will
replace the system
mask in the
current PSW
I
Ignored
Given the following Set System Mask
Instruction (in hex), the binary list
bit structure that will be placed in
bits 0-7 of the current PSW is 11110000.
o
r----T------
--~----,
I
80
I
00
0
I
0021
Set System
Mask
l ____
~
_______
~
___ J
7
r-----------,
0000
I
00
I
0001
I
FF
I
0002
I
FO
I
0003 I OF
I
0004
I
AA
I
L __________ J
Main Storage
SET PROGRAM
MAS~
INSTRUCTION
•
•
The Set Program Mask instruction is
used to change the setting of the
condition code and program mask in
the current PSW.
Set Program Mask is of the RR
format.
The R2 field is ignored.
The Set Program Mask instruction is of
the RR format.
r-----T----~-----,
I
04
I
R1
I
R2
I
L ____
~..;
____
~
_____ J
t
t
t
I
I
I
I
I
I
Set
I
I
Ignored
Program-~---J
I
Mask
I
I
I
I
Bits 2-7 of this reg-
ister replace the
condition code and
program mask bits
(34-39) of the current
PSW
Example:
r---~----T----'
Instruction
I 04
I
A
IB
I
L ___
~
____
~
____ J
r----T----T----~---,
Reg B
I FF I FF I FF
I
FF I
l __
~
____
~
____
~
____
J
r----T----T----T----'
Reg A
I
OF
I
OF I OF I OF I
L-Tr~----~---~----J
II
II
IL....,;--------,
I
I
I
I
l -__ ,
I
I
I
I
I
001111 I
I
I
I
I
PSW
I
I
r------T----T------~-t_T----t--------....,;,
I
System
I
IInter- IIICIProgllnstruc- I
IMask
I
IruptionlLICIMaskltion
I
I
I
I Code
ICI I
IAddress
I
l -_ _ _
~
___
~
______
~~~
____
J. _________
J
34 39
As can be seen in the above example,
reg B was ignored.
Bits 2-7 (001111) of
reg A were placed in positions
34-39
of
the PSW.
This action replaced the con-
dition code and prograF mask.
With a
program mask of all ones, any fixed
point and decimal overflows would be
treated as errors and a program inter-
rupt would occur.
1-67
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