Advertisement
The other priorities are shown top to
bottom in order of importance.
As an
example: AND number four must be satis-
fied to enter the micro program that
handles a memory wrap condition (X2
wrap).
The X-register is set, 0010000.
The inputs to this AND are:
1.
not priority latch - This line
blocks the AND
i f
there is another
priority in process.
2.
not gate switches to WX.
3.
not PP 1-2-3 - This input aSsureS
that no higher priority must be
taken first.
PPl is an output from
AND circuit number 1.
PP2 is an
output from AND number 2, etc.
4.
m.em.ory-wrap-request latch - This
line is developed from a priority-
stacking latch, which was set
because of a memory-wrap condition.
5.
not H-register 2 - There are times
when a memory wrap can occur but may
be ignored.
The micro program can
set position 2 of the H-register.
When this position is set, memory
wraps are ignored.
Two other lines are developed when
there is a priority entry; they are:
ALLOW LOW PRIORITY:
Active on priority,
PPl-2-3 or 4.
Used to satisfy lower
order priorities.
ANY PRIORITY PULSE:
Active when any
priority, PP1 through 8, is active.
This line is used to set a latch which
block further priorities, and is dis-
cussed later.
PRIORITY STACI< LATCHES AND CONTROLS
TheAND·s that develop the priority
pulses each have an input that is satis-
fied by a stacking latch (Figure 3-57).
These latches are needed because several
priorities may occur at one time, but
only one can be handled.
Notice that to
set tbe stacking latch for a MPX-share
request (PH1), position 6 of the H-
3-78
register must not be set.
Early in the
MPX-share request micro program, this
position of the H-register is set.
Further MPX-share requests are then
blocked from setting the stacking latch.
When there is a.selector-channel-ROS
request, the micro program that handles
the request sets position 5 of the H-
register.
This not only blocks further
selector-channel ROS-requests, but also
MPX-channel-share requests.
While one priority is being handled,
others must be temporarily blocked.
Remember, if a priority pulse is
developed, the line (any-priority-pulse)
is active.
This line turns on the any-
priority latch at Tl time.
With this
latch on, a T3 pulse turns on the
priority latch.
The priority latch,
when it is on, blocks the AND circuits
that develop further priority pulses
until the latch is reset.
Some of the
ways to reset the priority latch are:
1.
At Tl time, with a
process-stop~loop
active.
This line is active when
the mnemonic S STOP is encountered
in the micro program.
2.
At P4 time, with the WX SABC latch
on.
This latch is turned ON at Tl
time if WX must be set manually.
3.
At T3 time, if the
priority-reset-control latch is on.
This latch is set on when the H-
register is specified as the
destination of data (eg.
A
+
B
->H) •
REVIEW QUESTIONS--FORCED MICROPROGRAM
ENTRIES
1.
What address is set in ROAR for MPX
share request?
2.
Which function has highest priority?
3.
Priorities are stored while awaiting
execution by means of
latches.
4.
How is the priority reset control
latch turned on?
Advertisement
