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REGISTERS
•
The registers of the CPU are storage
latches.
•
polarity Hold latches and AOI latch-
es are used.
•
Register input and output lines are
controlled by ROS.
Registers have been described in the
section on Data Flow as address reg-
isters, data registers, status registers
and other general use registers.
These
registers are storage latches wbich can
accept information, store the informa-
tion and then read out the information,
without destroying the data
(nondestructive read out).
All of these
functions are under control of the ROS
which supplies gates and pulses to allow
movement of the data from one location
to another.
There are two types of latches used
in the 2030 Processor.
The first and
most frequently used is the Polarity
Hold latch.
Reviewing briefly the PH
latch, the output line follows the data
line when the control line is active.
This means then, that the information on
the data lines will be set into the
register when the control line is
brought up.
One example of register operation,
which is similar to most registers using
a PH circuit, is the R-register.
This
register has two input sources and three
major destinations.
(See Figure
2-18)
One input comes from the main storage
unit" consists of 9 bit lines (8
+
parity)" and is labeled Storage Data
out
bit.
This input is gated
into the latches by memory set R.
The
control line is Set R-register (Figure
2-34)
oj
The second input is from the Z-bus
and is labeled accordingly.
The bits on
this bus are gated into the R-register
by Z-bus set R and the control line Set
R-register.
2-22
Z-bus 0 Bit.
Z-.bus Set R.
A
Storage Data Out 0 Bit
t----
0
Memory Set R
A
R
"0" Bit
Set R-register
(control)
---PH---
R-register
(8 Bits
+
Parity.
One position shown)
Basic CA Decode-
Not CA Zero
A
L- .
-
A
A-bus Zero Bit
CA 1
ICA 7
OR
CA 2
r-
~
CA 3
~
~
Set R-register Manually
Figure 2-34.
R-Register Zero-Bit
Latch
All of the nine PH latches in the
R-register turn on as described above.
However, the parity latch has one addi-
tional turn on, which would not be pre-
sent on other registers and is therefore
not shown in Figure 2-34.
In order to
prevent an R-register parity check at T2
time, the parity latch is turned on by a
line which comes from the machine reset
circuitry.
This prevents a completely
blank R-register from turning on the
Machine Check 6 latch at T2 time or
after a machine reset.
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