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Store Bit-Lines
N-Reg 4
N-Reg 5
N-Reg 6
N-Reg 7
The nine store bit-lines provide the
data input to the core-storage unit.
These lines are direct outputs of the
R-register, and they go to the core
storage inhibit drivers.
The nine store
bit-lines are:
Store parity Bit
Store 7 Bit
Store 6 Bit
Store 5 Bit
Store 4 Bit
Store 3 Bit
Store 2 Bit
Store 1 Bit
Store 0 Bit
Memory Sense Bit-Lines
These nine lines represent the core-
storage data output.
They are active at
memory strobe time, which is 525-800
nanoseconds of the memory read cycle.
If the data on the memory sense bit-
lines is to be used by the CPU, the
melllory clock data ready pulse (750-900)
is allowed to set the appropriate R-
register latches from the data on the
sense lines.
The nine sense bit-lines
present at the R-register input are:
Mem Sense Parity Bit
Mem Sense O-bit
Melli Sense 1-bit
Melli Sense 2-bit
Mem Sense 3-bit
Mem Sense 4-bit
mem Sense 5-bit
Mem Sense 6-bit
Mem Sense 7.,.bit
Early MO
The memory clock must be started at the
beginning of T1 time so the CPU and
memory stay in step.
Selection of the
first 32K clock or second 32K clock is
dependent on the high-order position of
the M-register (M-reg O-bit).
However,
the MN-register set pulse is at Tl tillie,
and it takes approximately 50
nanoseconds to set the MN-register
latches.
This would not allow the M-
register a-bit to start either of the
two memory clocks at zero time in the
CPU clock cycle.
The early-MO pulse
occurs before the M-register has set,
and is actually before zero time in the
CPU clock cycle.
If the early-MO signal
is present at the clock control
circuitry at zero time of the CPU clock
cycle, the CPU read-call signal starts
the second 32K clock.
If early-MO is
not present when the CPU read-call sig-
nal arrives, the first 32K clock is
started.
Early-MO is not brought up for a
write cycle because the MN-registers are
not changed for a memory write cycle.
For a write cycle, the M-register O-bit
line switches with the CPU write-call
signal to control the two clocks.
Early Local Storage
The function of this signal is similar
to that of early-MO: control of the two
memory clocks.
Early local storage
occurs before zero time in the CPU clock
cycle to signal the memory that the next
access to memory will
be
in the first
32R.
When read call occurs, the first
32K clock starts.
Read Call
Read-call signals the memory that the
CPU control circuitry has decoded a read
operation.' The read-call pulse occurs
at
Tl~time
of the CPU clock cycle and it
is used to start the memory clock.
Read-call specifies a memory-read cycle
by setting up the memory clock for a
read operation (Figure 2-55).
Write Call
Write-call occurs at T1 time of the next
cycle after the CPU control circuitry
has decoded a write operation. Write-
call starts the memory clock, and
specifies a memory-write cycle by set-
ting up the memory clock for a write
operation (Figure 2-55).
Data Ready
Data-ready is the memory data strobe
pulse to the CPU.
.At 750-900 nanose-
conds of the memory clock read cycle,
the data- ready 'signal sets the data or
the memory sense bit lines into the
R-register, providing the CPU has speci-
fied memory as the source for the R-
register.
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