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r---,.------,
I
0
I
1022
I
L __
-I. ______
J
t
t
I
t
I
1
I
. 1
Base
Displacement
Reg.
Contents of Reg. 0 is
,--,
120481
L ____ J
Given the above address portion in
the instruction and the contents of
Register 0, the effective storage
address would
be
1022.
Because register
o
was specified as the Base Register, a
Base Address of 0 is used.
The contents
of Reg.
0 is ignored.,
All storage addresses are generated
by using base and displacement.
In some
instructions, however, a third factor is
used.
The third factor is called the
Index value.
It is also contained in a
General Register.
In those instructions that include an
indexing
facto~,
the address portion
looks like this:
r-----~---T------------,
I
Index
I
Base
I
Displacement
I
I
Reg·IReg.
I
I
IAddr·IAddr·1
1
L-_ _
~
___
~
___________ J
4
4
12 bits
The effectiVe storage address would be
generated by adding:
1.
Displacement.
2.
Contents of Base Register.
3.
Contents of Index Register.
For example, suppose the address portion
of an instruction is as follows:
'--T--T------. . . -
,
I
6
I
7
I
1012
t
L-__
..&.-.-~
_________
J
Register 6 contains the value 2048, and
register 1 contains the value 6024.
We
can derive the following values:
1.
The effective storage address is
9084.
2.
The address portion of the instruc-
!!2n
is unchanged.
3.
The values in the base and index
registers are unchanged.
Thus the only thing we did was generate
a storage address by adding the contents
of the base register (6024) plus the
contents of the index register (2048) to
the displacement value given in the
instruction (1012).
The values in the
specified registers remain unchanged, as
does the displacement value in the
instruction remain unchanged.
INSTRUCTION FORMATS
•
There are 5 basic instruction for-
mats.
•
•
•
They are RR, RX,
RS ,
S1 and SS
r------,.--,.--,
RR Op CodelR11R21
L _______
.L __ .L __
J
r------,.--,.--,.-~--,
RX Op CodelRl1X21B21D21
L _______
.L __ .L_-.L __ .L __
J
r------T--T--~-T--'
RS Op CodelRl1R31B21D21
L ______
-.L __ .L_-.L--.L __
J
r-------,.-----,.--T--'
S1 I Op Code 1 12
I B 11 D 11
L--_____ .L _____ .L-_.L-_J
r-------T--T--,.--,.--T--T--'
SS 1
Op
Codet L 11 L21 B 11 D 1
J
B21 D21
L _ _ _ _
.L_.L--.L-_.L __ .L-_.L-J
In most operations, the first oper-
and (R 1 or B1, Dl) is replaced
by
the results or the contents of the
second operand (R2, 12 or ·B2, D2).
The number in the length code in the
SS format is always one less than
the true length of the data field.
Let's take a look at the instruction
formats of the System/360.
As you know,
the instructions are of 3 lengths:
1, 2
or 3 halfwords depending on the location
of the operands.
RR FORMAT:
A l--halfword instruction is
used when both operands are in two gen-
eral registers or in two floating point
registers.
What is required is:
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