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(Not) Inh ROAR Set
-
ot) Inhibit ROAR Set
(N
( Not) Block W-Reg Set
A
---<
Any Priority Pulse
Gt UV to WX
Gt CA to W
A
t--
' - - -
A
-
OR
Gt BU ROAR to WX
Gt CKto W Reg
-
Figure 3-41.
WX Register Sets
See Figure 3-40
(5).
There are also
backup positions for branching.
X6
and
X7 backup latches are necessary because
of timing considerations.
Specific controls for ROAR and indi-
cating ROAR are shown in Figure 3-41 and
3-42.
Check Stop Sw
ALU Chk
C'hTReg. Chk.
,:"M,:,-N.;,;;Re;,,:g' , :-:C::;;h;,:.:kO _ _
-l
OR
B-Reg
°
Chk
°
A-Reg
°
Chk
°
Allow A-Reg. Chk.
A
A
A
T4
Figure 3-42.
Set Indicating RCAR
REVIEW QUESTICNS - ROAR CONTRCLS
Set WI - XI
1.
How is position 3 of the W-register
set when the mnemonic CA->W us used?
2.
What console switches are used to
set ROAR?
3.
Which control field sets positions
0-5 of the X-register?
4.
What address is set in RCAR as a
result of a machine check?
5.
There are console lights that indi-
cate the status of ROAR.
TRUE
FALSE
A
X-Reg
-
OR
Set
' - -
Tl
-
W-Reg
OR
Set
-
~
' - -
A
OR
-
- -
6.
An ALU check blocks the set of the
indicating ROAR.
TRUE
FALSE
RCS TIMINGS
•
ROAR is set at Tl time.
•
The CPU GC pulse is used to develop
the RCAR read out pulse.
•
The SAL'S are good at T4 time.
•
The control registers are set at T1
time.
•
Backup ROAR is set at T4 time.
The ROS timings may be divided into
three groups:
1.
Basic
2.
Micro Program Break In
3.
Parity Check
BASIC TIMINGS
Figure 3-43 shows the basic timings
associated with RCAR.
Two 1-microsecond
ROS cycles are represented.
Each cycle
is divided
by
the CPU times Tl, T2, T3,
and T4.
3-63
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