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(Not) N-Reg 3-Bit
(Not) N-Reg 2-Bit
Not Used
Read I 0-161<
X READ DRIVER MS061
N-Reg 7-Bit
Not Used
N-Reg 6-Bit
Nat Used
+18
+18
(Not) N-Reg 5 and 4 Bit
<>--------'
X GATE DeCODE MS021
M-Reg 5-Bit
(Not) M-Reg 4-Bit
(Not) M-Reg 3-Bit
R2-8+24K -W2-16+32K
Y READ DRIVER MSIOI
X READ GATE TRANSISTOR MS391
:;:;::::~W~;:<::'::'::':;·W":·:::-:':':':'::::l::::::::::i::::::::~;::~::::::::::;':::=::::::;;;::::;:::::::::::::::'<:}}:::·""""'''~''''''+O'':!'''''''''';'''''''''~+I~;;'8'''''C'1,'a''m'''pedm,;:
(Not) N-Reg I-Bit
Not Used
N-Reg O-Bit
Not Used
M-Reg 7-Bit and
(Not) M-Reg 6-Bit
y
GATE
DECODE~MS031
+V
Y READ GATE TRANSISTOR MS421
Figure 2-61.
Storage Read Example
Circuit Qbjectives (Figure 2-61)
1.
Start the clock for the first 32R
storage unit MS321) •
2.
3.
2-56
Start 1st 32R clock
(Not) Early MO eM-register O-bit)
Read Call
Define area of storage to be
addressed (MS321) •
Use Main Mem
(Not) Local St or MPX
Read Call
Decode and drive an X-line.
+40
+0
Phose Read B
rn-...--I~_-o
(Not) M-Reg 2-8it
Y READ GATE TERMINATOR MS151
Phase Read A
L!'J-...-IH,,""*--o
M-Reg I-Bit
X READ GATE TERMINATOR MS151
a.
Read 1 16-32K.
This read timing
pulse from the clock conditions
the proper X-drivers as required
by the phase reversal addressing
scheme (MS161).
b.
11
Read
1
(from clock)
M-Reg 1-bit (switched with
Use Main Mem)
Gate TX 16-32K.
This is the
X-gate decode (MS021) •
N-Reg 7-Bit
N-Reg 6-Bit
(Not) N-Reg 5-Bit
N-Reg 4-Bit
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