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(~ot)
~-Reg
5-Bit
~-Reg
4-Bit
c.
WRl 0-15 16-32K.
This is the X
driver decode (101S061).
Write
1
16-32K
(~ot)
~-Reg
2-Bit
(~ot)
N-Reg 3-Bit
d.
Ary Side A 15
X
Ln 11 Al.
This
is one end of the X-drive line
(101S381) •
11 Gate TX 16-32K
WRl 0-15 16-32K
e.
Write 16-32K.
This line pro-
vides a current path at the
other end of the X-line.
This
requires that the X write-gate
terminator be turned on
(MS
151) •
Phase Write A (from clock)
M-Reg l-Bit Controlled
X Gate Term Current Source
(from power supply)
4.
Decode and drive a Y-line.
a.
R2-16+32K-W2-8+24KA.
This write
timing pulse from the clock
conditions the proper Y-drivers
as required by the phase rever-
sal addressing scheme
161) •
(not) M-Reg 2-Bit
Write 2 (from clock)
Use Main Mem
b.
R-16+32K-W-8+24K-3072-4095.
This is the Y- driver decode
(101S091) •
(not) M-Reg 3-Bit
M-Reg 4-Bit
M-Reg 5-Bit
R2-16+32K-W2-8+24K A
c.
384-447 Gate TX Cl.
This is the
Y-gate decode (101S031).
(not) N-Reg 1-Bit
N-Reg O-Bit
M-Reg 7-Bit
(not) M-Reg 6-bit
d.
Ary Side D 99 Y Ln 54 C1.
This
is one end of a Y-drive line
(MS401) •
2-60
384-447 Gate TX C1
(conditions emitter of
write gate transistor)
R-16+32K-W-8+24K-3072-4095,
(conditions base of write
gate transistor)
e.
R-16+32K-W-8+24K.
This line
provides a current path at the
other end of the Y-drive line.
It is the result of the Y read
gate terminator being turned on
(MS 151) •
Y Gate Term Current Source
(from power supply)
Phase Write
A
(from clock)
M-Reg
~ot
2-Bit controlled
5.
Activate the appropriate inhibit
drivers.
For each core plane in an
8K unit there are two sense/inhibit
windings.
ThUS, there are 18
sense/inhibit windings in an 8K
block of storage.
To supply inhibit
current, there is one set of nine
inhibit current drivers for the one
half of the 8K block, and one set of
nine inhibit current drivers for the
other half of the 8K block (Figure
2-63).
Only one of these sets of
nine inhibit drivers is allowed to
be
active during any storage write
cycle.
This means that a set of
nine inhibit drivers lrust be select-
ed as a part of the address decode.
Thus, to store a properly coded byte
of information in an addressed posi-
tion, the proper set of nine inhibit
drivers must be conditioned to turn
on.
Then the bit coding of the byte
to be stored causes the correct
inhibit drivers of that set to be
turned on at inhibit time.
For each
bit position of the byte to be
stored, presence of a bit at the
inhibit driver input prevents that
inhibit driver from turning on.
Conversely, for each bit position of
the byte to be stored, absence of a
bit allows the inhibit driver to
turn on.
As a result, there is no
inhibit current flowing where a bit
is to be stored, and inhibit current
flows where no bit is to be stored.
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