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The M2-I uses combination sense/inhibit
windings for storing and retrieving infor-
mation.
This winding is wound parallel to
the X-winding and it goes through 4096
cores in a single core plane.
There are
four such windings for each l6,384-core
plane.
During a read cycle, a core that
switches (was logical 1) induces a pulse
onto the sense/inhibit winding.
This
pulse is amplified by a sense amplifier
(Figure 2-77).
The sense amplifier senses
a change or difference in current on the
sense winding and is called a differential
amplifier.
To prevent unwanted noise from
being amplified in other storage sections,
only the sense winding outputs for the
4,096 block of storage being addressed are
allowed to reach sense amplifiers.
The
sense amplifier gate allows the desired
sense winding output to reach sense ampli-
fiers.
The output of the sense amplifiers
appears at the input of the detector cir-
cuit.
Here the strobe pulse from the
U61CD
+6
+6
__ I __ _
•
Not-Bit
A
Driver
Circuit
storage clock gates the sense amplifier
output to a data latch which stores the bit
until used by the processing unit.
During
a read cycle, if a core does not switch
(was logical 0), no pulse is induced onto
the sense winding, and therefore the data
latch is not set.
During a write cycle, if a bit is to be
stored in a core, the core is switched by
the effect of the coincident X and Y drive
currents.
In this case, the inhibit cur-
rent is not allowed to flow (Figure 2-77).
During a write cycle, if the bit is to be
blocked from setting, inhibit current must
flow to oppose the magnetic effect of the
X-winding.
With no bit present at the in-
hibit drive input, the inhibit driver turns
on, inhibit current flows and the effect of
the inhibit current cancels the effect of
the X winding current.
As a result, the
core is not set.
Sense/Inhibit Winding
4096 Cores
Parallel to X-Winding
Pre - Amp Gate ______
~Sense
Amplifier
Use This
4K
Block
1-- - - - --
1
U61CG
:
UcrJAV,AW
Ul6AX
.....
-:---I~
:
--I
-30o--.....
--+-........
I
I
1
I
1-- - - ---
I
1
1~6!ES
_ _ _ I
Figure 2-77.
Sense and Inhibit Logic
Strobe _ _ _
~
Detector
U07AT,AU
Reset ___ _ ......
_EL __
U03DP
U03DQ
U03AF
Bit
2-77
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