Advertisement
Address
Selection
and Drive
64X
Lines
Figure 2-51.
Composite Core Layout
must be made to flow in the 3-, 4-, 6-,
and 7-bit core planes so the 3-, 4-, 6-,
and 1-bit cores in the addressed posi-
tion are not set (Figure 2-51).
In the 2030 core-storage unit, each
core plane has two sense-inhibit wind-
ings.
Each winding is threaded through
4,096 cores.
The two windings are func-
tionally the same.
However, using two
windings for
ea~h
core plane relaxes the
design requirements for each inhibit
current driver and sense amplifier, and
provides more reliable operation.
8K AUXILIARY STORAGE
•
•
•
•
2-40
Added area for CPO, and I/O control
and status information.
Additional addressing inY-dimension
only.
Main-Auxiliary latch in CPO defines
area to be addressed
M-register 3-bit selects CPO local
or MPX storage
Included in the 8,192-position storage
unit is an additional 512-position aux-
iliary storage section.
In this
section, 256 positions are reserved for
Use by the multiplexor channel.
The
other 256 positions of local storage are
used
by
the CPU for special and general
purpose registers (Figure 2-52).
The additional 512 storage positions
are formed by adding eight lines in the
Y-direction (eight Y-lines intersect
with 64 X-lines produce 512 additional
storage positions).
Eight Y read-gate
transistors provide read current for the
eight auxiliary Y-lines, while eight
write- transistors provide write current
for the auxiliary Y-lines.
At each end of the auxiliary Y-lines,
the auxiliary gate-transistors are con-
trolled by the y-gate decode-switches
and two special auxiliary drivers.
When
an address in the range of 000-255 is
placed in the MN-register, it refers to
one of three storage positions.
The
desired position may be in main storage,
CPU local storage, or multiplexor stor-
age.
To select which of the three areas
is to be addressed, a latch in the CPU
Advertisement
